First, the construction of a conventional flash memory device will be explained with reference to FIG. 1 showing the concept of a generally used flash memory device having a so-called stacked gate structure.
Referring to FIG. 1, the flash memory device is constructed on a silicon substrate 1700 and includes a source region 1701 and a drain region 1702 formed in the silicon substrate 1700, a tunneling gate oxide film 1703 formed on the silicon substrate 1700 between the source region 1701 and the drain region 1702, and a floating gate 1704 formed on the tunneling gate oxide film 1703, wherein there is formed a consecutive stacking of a silicon oxide film 1705, a silicon nitride film 1706 and a silicon oxide film 1707 on the floating gate 1704, and a control gate 1708 is formed further on the silicon oxide film 1707. Thus, the flash memory of such a stacked structure includes a stacked structure in which the floating gate 1704 and the control gate 1708 sandwich an insulating structure formed of the insulation films 1705, 1706 and 1707 therebetween.
The insulating structure provided between the floating gate 1704 and the control gate 1705 is generally formed to have a so-called ONO structure in which the nitride film 1706 is sandwiched by the oxide films 1705 and 1707 for suppressing the leakage current between the floating gate 1704 and the control gate 1705. In an ordinary flash memory device, the tunneling gate oxide film 1703 and the silicon oxide film 1705 are formed by a thermal oxidation process, while the silicon nitride film 1706 and the silicon oxide film 1707 are formed by a CVD process. The silicon oxide film 1705 may be formed by a CVD process. The tunneling gate oxide film 1703 has a thickness of about 8 nm, while the insulation films 1705, 1706 and 1707 are formed to have a total thickness of about 15 nm in terms of oxide equivalent thickness. Further, a low-voltage transistor having a gate oxide film of 3–7 nm in thickness and a high-voltage transistor having a gate oxide film of 15–30 nm in thickness are formed on the same silicon in addition to the foregoing memory cell.
In the flash memory cell having such a stacked structure, a voltage of about 5–7V is applied for example to the drain 1702 when writing information together with a high voltage larger than 12V applied to the control gate 1708. By doing so, the channel hot electrons formed in the vicinity of the drain region 1702 are accumulated in the floating gate via the tunneling insulation film 1703. When erasing the electrons thus accumulated, the drain region 1702 is made floating and the control gate 1708 is grounded. Further, a high voltage larger than 12V is applied to the source region 1701 for pulling out the electrons accumulated in the floating gate 1704 to the source region 1701.
Such a conventional flash memory device, on the other hand, requires a high voltage at the time of writing or erasing of information, while the use of such a high voltage tends to cause a large substrate current. The large substrate current, in turn, causes the problem of deterioration of the tunneling insulation film and hence the degradation of device performance. Further, the use of such a high voltage limits the number of times rewriting of information can be made in a flash memory device and also causes the problem of erroneous erasing.
The reason a high voltage has been needed in conventional flash memory devices is that the ONO film, formed of the insulation films 1705, 1706 and 1707, has a large thickness.
In the conventional art of film formation, there has been a problem, when a high-temperature process such as thermal oxidation process is used in the process of forming an oxide film such as the insulation film 1705 on the floating gate 1704, in that the quality of the interface between the polysilicon gate 1704 and the oxide film tends to become poor due to the thermal budget effect, etc. In order to avoid this problem, one may use a low temperature process such as CVD process for forming the oxide film. However, it has been difficult to form a high-quality oxide film according to such a low-temperature process. Because of this reason, conventional flash memory devices had to use a large thickness for the insulation films 1705, 1706 and 1707 so as to suppress the leakage current.
However, the use of large thickness for the insulation films 1705, 1706 and 1707 in these conventional flash memory devices has caused the problem in that it is necessary to use a large writing voltage and also a large erasing voltage. As a result of using large writing voltage and large erasing voltage, it has been necessary to form the tunneling gate insulation film 1703 with large thickness so as to endure the large voltage used.